As switching power circuits, those adopting a switching converter of, for example, a fly-back converter type, a forward converter type or the like are widely known. In these switching converters, the switching operation waveform is a rectangular waveform and, therefore, there is a limitation in suppressing the switching noises. In addition, due to their operation characteristics, it is known that there is also a limitation in enhancing the power conversion efficiency.
In view of the foregoing, a variety of switching power circuits based on a resonance type converter have been proposed and put to practical use. The resonance type converter makes it possible to easily obtain a high power conversion efficiency, and to realize a low-noise property because the switching operation waveform is a sinusoidal waveform. Besides, the resonance type converter has the merit that it can be composed of a comparatively small number of component parts.
The circuit diagram shown in FIG. 27 shows one example of a switching power circuit including a resonance type converter, as an example of the prior art. In the power circuit shown in this figure, a separately excited current resonance type converter is combined with a partial voltage resonance circuit.
In the power circuit shown in the figure, first, for a commercial AC power source AC, a full-wave rectifying and smoothing circuit composed of a bridge rectification circuit Di and one smoothing capacitor Ci is provided. The full-wave rectifying operation of the bridge rectification circuit Di and the smoothing capacitor Ci produces a rectified and smoothed voltage Ei (DC input voltage) between both ends of the smoothing capacitor Ci. The rectified and smoothed voltage Ei is at a level corresponding to the equal fold of the AC input voltage VAC.
A current resonance type converter for performing switching by being supplied with the DC input voltage is composed by connecting two switching devices Q1, Q2, which are composed of MOS-FETs, in half-bridge coupling, as shown in the figure. Damper diodes DD1, DD2 composed of body diodes are connected in parallel between the respective drain and source of the switching devices Q1, Q2, according to the direction shown in the figure.
In addition, a partial resonance capacitor Cp is connected in parallel to the portion between the drain and source of the switching device Q2. The capacitance of the partial resonance capacitor Cp and the leakage inductance L1 of the primary winding N1 form a parallel resonance circuit (partial voltage resonance circuit). As a result, there is obtained a partial voltage resonance operation showing a voltage resonance only when the switching devices Q1, Q2 are turned OFF.
In this power circuit, an oscillating drive circuit 2 composed of a general-purpose IC, for example, is provided for driving the switching of the switching devices Q1, Q2. The oscillating drive circuit 2 has an oscillating circuit and a drive circuit. The oscillating circuit and the drive circuit operate to impress a drive signal (gate voltage) at a required frequency on each of the gates of the switching devices Q1, Q2. This ensures that the switching devices Q1, Q2 perform switching operations so that they are alternately turned ON/OFF at a required switching frequency.
An insulated converter transformer PIT transmits the switching outputs of the switching devices Q1, Q2 to the secondary side. One end of the primary winding N1 of the insulated converter transformer PIT is connected to the connection point (switching output point) between the source of the switching device Q1 and the drain of the switching device Q2 through series connection of a primary-side parallel resonance capacitor C1, whereby the switching outputs are transferred.
Besides, the other end of the primary winding N1 is connected to a primary-side earth.
Here, the capacitance of the series-connected resonance capacitor C1 and the leakage inductance L1 of the insulated converter transformer PIT including the primary winding N1 form a primary-side series resonance circuit for causing the operation of a primary-side switching converter to be of a current resonance type.
According to the foregoing, with the primary-side switching converter shown in this figure, there are obtained an operation of the current resonance type by the primary-side series resonance circuit (L1-C1) and a partial voltage resonance operation by the above-mentioned partial voltage resonance circuit (Cp//L1).
In other words, the power circuit shown in the figure adopts a type in which a resonance circuit for causing the primary-side switching converter to be of the resonance type is combined with another resonance circuit. Such a switching converter as this will hereinafter be referred to as a compound resonance type converter.
Though illustration is omitted here, as a structure of the insulated converter transformer PIT, for example, an EE type core formed by combining E type cores formed of ferrite material is provided. Then, the primary winding N1 and a secondary winding (N2A, N2B) which will be described next are wound around a center magnetic leg of the EE type core while the winding portions are divided on the primary side and on the secondary side.
As the secondary winding of the insulated converter transformer PIT, the secondary windings N2A, N2B bisected by center tapping are wound. In the secondary windings N2A, N2B, alternating voltages according to the switching outputs transferred to the primary winding N1 are excited.
In this case, the center tap between the secondary windings N2A, N2B is connected to a secondary-side earth. A full-wave rectification circuit composed of rectifying diodes D01, D02 and a smoothing capacitor C0 is connected to the secondary windings N2A, N2B, as shown in the figure. This ensures that a secondary-side DC output voltage E0 is obtained as the end-to-end voltage of the smoothing capacitor C0. The secondary-side DC output voltage E0 is supplied to the side of a load (not shown), and is shuntedly inputted as a detection voltage for a control circuit 1 which will be described next.
The control circuit 1 supplies the oscillating drive circuit 2 with a detection output according to a variation in the level of the secondary-side DC output voltage E0. The oscillating drive circuit 2 drives the switching devices Q1, Q2 in such a manner that the switching frequency is varied according to the detection output of the control circuit 1 inputted thereto. With the switching frequency of the switching devices Q1, Q2 thus varied, the level of the secondary-side DC output voltage is stabilized.
Operation waveforms in the case where the power circuit configured as shown in this figure is operated under a low-voltage large-current load condition are shown in FIG. 28. The operation waveforms shown in FIG. 28 were obtained by measurements under the conditions of an AC input voltage VAC=100 V and a load power P0=100 W. Here, the low-voltage large-current condition is a condition where the secondary-side DC voltage is E0=5 V and the primary-side series resonance current, which is the switching current of the primary-side switching converter, is I0=25 A.
In addition, the experimental results concerning the operation waveforms shown in FIG. 28 were obtained under the following conditions and the following settings of the component parts of the power circuit and the like.
First, the numbers of turns of the secondary windings N2A, N2B and the primary winding N1 are so set that the induced voltage level per T (turn) of the secondary-side winding is 5 V/T; specifically, the secondary windings N2A=N2B=1 T, and the primary winding N1=30 T.
Besides, a gap of about 1.0 mm is formed at the center magnetic leg of the EE type core of the insulated converter transformer PIT. This leads to a coupling coefficient of about 0.85 between the primary winding N1 and the secondary windings N2A, N2B.
In addition, the primary-side series resonance capacitor C1=0.068 μF and the partial voltage resonance capacitor Cp=330 pF are selected, and 50 A/40 V Shottky diodes are selected as the rectifying diodes D01, D02.
In the waveform diagrams shown in FIG. 28, the end-to-end voltage V1 of the switching device Q2 corresponds to the ON/OFF condition of the switching device Q2. Specifically, the end-to-end voltage V1 assumes the form of a rectangular wave being at zero level over the period T2 in which the switching device Q2 is ON and being clamped at a predetermined level over the period T1 in which the switching device Q2 is OFF. As for the switching current IDS2 flowing through the switching device Q2//damper diode DD2, it is in negative polarity by flowing through the damper diode DD2 at the time of turning ON, is then inverted to positive polarity and flows along the drain→source of the switching device Q2, as shown in the period T2; in the period T1, it is at zero level due to turning-OFF.
In addition, the switching device Q1 performs switching so as to be turned ON/OFF alternately relative to the switching device Q2. Therefore, the switching current IDS1 flowing through the switching device Q1//damper diode DD1 assumes a waveform with a phase shift of 180° relative to the switching current IDS2.
The primary-side series resonance current I0 flowing through the primary-side series resonance circuit (C1-L1) connected to a point between the switching output point of the switching devices Q1, Q2 and the primary-side earth assumes a waveform obtained by composing a sinusoidal wave component as the resonance current of the primary-side series resonance circuit (C1-L1), which corresponds to the composite waveform of the switching current IDS1 and the switching current IDS2, with a sawtooth wave component generated by the excitation inductance of the primary winding N1.
In this case, the measurement condition, i.e., the load power P0=100 W, is a heavy load condition approximate to the maximum of the load condition for the power circuit shown in FIG. 27; under the condition tending to take such a heavy load within the relevant load power range, the rectified current on the secondary side is in a discontinuous mode.
Thus, as shown in FIG. 28, the secondary winding voltage V2 generated in the secondary winding N2A has a waveform being clamped at a predetermined absolute value level only over the period in which the primary-side series resonance current I0 flows in the sinusoidal waveform and being at zero level over the period in which the sawtooth wave component due to the excitation inductance flows as the primary-side series resonance current I0. In the secondary winding N2B, a waveform obtained by inverting the secondary winding voltage V2 is generated.
Therefore, the rectified current I1 flowing through the rectifying diode D01 and the rectified current I2 flowing through the rectifying diode D02 flow respectively in the periods DON1, DON2 in which the primary-side series resonance current I0 flows in the sinusoidal waveform, and neither of them flows during the other periods. Namely, the rectified currents on the secondary side flow discontinuously into the smoothing capacitor.
The forward voltage drop of the rectifying diodes D01, D02 composed of Shottky diodes is 0.6 V, and, in the secondary-side operation as above-mentioned, the rectified currents I1, I2 are on a fairly high level of 35 Ap, as shown also in the figure; therefore, the conduction loss due to these rectifying diode devices is conspicuous, resulting in a large power loss. As an actual measurement result, the DC→DC power conversion efficiency at the time of the DC input voltage (rectified and smoothed voltage Ei)=100 V remains at about 82%.
In view of this, as a technology for reducing the conduction loss of the rectified current on the secondary side, there is known a synchronous rectification circuit in which rectification is performed by a low-ON-resistance MOS-FET. As such a synchronous rectification circuit, an example of the configuration based on a winding voltage detection system is shown in FIG. 29.
Incidentally, in FIG. 29, only the configuration on the secondary side of the insulated converter transformer PIT is shown. The configuration on the primary side is assumed to be the same as in FIG. 27. In addition, as a constant voltage control system, there is adopted a switching frequency control system in which the switching frequency of the primary-side switching converter is variably controlled according to the level of the secondary-side DC output voltage E0.
Besides, as the power circuit adopting the secondary-side configuration shown in FIG. 29, one which corresponds to the same low-voltage large-current condition (VAC=100 V, load power P0=100 W, E0=5 V, I0=25 A) as in the case of FIG. 27 is adopted.
In this case also, one-side ends of the secondary windings N2A, N2B having an equal number of turns are connected by the center tap, and the center tap output is connected to the positive terminal of the smoothing capacitor C0. The other end of the secondary winding N2A is connected to the secondary-side earth (the negative terminal side of the smoothing capacitor C0) through the drain→source of an N-channel MOS-FET Q3. Similarly, the other end of the secondary winding N2B is also connected to the secondary-side earth (the negative terminal side of the smoothing capacitor C0) through the drain→source of an N-channel MOS-FET Q4. In this case, in each of the rectification current paths of the secondary windings N2A, N2B, the MOS-FET Q3, Q4 is inserted in series with the negative electrode side. Incidentally, body diodes DD3, DD4 are connected between the respective drain and source of the MOS-FETs Q3, Q4.
A drive circuit for driving the MOS-FET Q3 is formed by connecting a gate resistance Rg1 between the connection point between the secondary winding N2B and the drain of the MOS-FET Q4 and the gate of the MOS-FET Q3, and connecting a resistance R11 between the gate of the MOS-FET Q3 and the secondary-side earth.
Similarly, a drive circuit for driving the MOS-FET Q4 is formed by connecting a gate resistance Rg2 between the connection point between the secondary winding N2A and the drain of the MOS-FET Q3 and the gate of the MOS-FET Q4, and connecting a resistance R12 between the gate of the MOS-FET Q4 and the secondary-side earth.
When an ON voltage is impressed on the gate of a MOS-FET, the drain-source portion becomes equivalent to a mere resistor, so that currents can flow in both directions. In order to make this function as a rectifying device on the secondary side, a current must be made to flow only in the direction for charging the positive terminal of the smoothing capacitor C0. If a current flows in the direction reverse to this, a discharge current flows from the smoothing capacitor C0 to the side of the insulated converter transformer PIT, so that power cannot be effectively transferred to the load side. In addition, the reverse current causes heat generation in the MOS-FET, noises and the like, leading to a switching loss on the primary side.
The above-mentioned drive circuits are for driving the switching of the MOS-FET Q3, Q4 in such a manner that a current flows only in the direction for charging the positive terminal of the smoothing capacitor C0, based on the detection of the voltages of the secondary windings.
The waveform diagrams in FIG. 30 correspond to the operation of a power circuit, adopting the secondary-side configuration shown in FIG. 29 (the primary side is the same as in FIG. 27), under the condition of a load power P0=100 W. As has been mentioned above, the load power P0=100 W in this case is a substantially maximum load condition.
In this figure, the end-to-end voltage V1 of the switching device Q2 and the secondary winding voltage V2 obtained between both ends of the secondary winding N2A-N2B corresponding thereto are at the same timings as in FIG. 28. Incidentally, the secondary winding voltage V2 sown in FIG. 30 is in the polarity as viewed from the side of the connection point between the secondary winding N2A and the gate resistor Rg2, and the polarity is inverted when viewed from the side of the connection point between the secondary winding N2B and the gate resistor Rg1.
When a period in which the secondary winding voltage V2 in the polarity shown in this figure is clamped at a predetermined level in negative polarity is reached, the drive circuit for the MOS-FET Q4 operates so as to impress on the gate of the MOS-FET Q4 an ON voltage at a level set by the gate resistor Rg2 and the resistor R12.
Similarly, when a period in which the secondary winding voltage (V2) in the inverted polarity relative to the polarity shown in the figure is clamped at a predetermined level in negative polarity is reached, the drive circuit (the gate resistor Rg1 and the resistor R11) for the MOS-FET Q3 operates so as to impress an ON voltage on the gate of the MOS-FET Q3.
As a result, rectified currents I1, I2 in positive polarity flow through the MOS-FETs Q3, Q4 in periods DON1, DON2, respectively as shown in the figure. The rectified currents I1, I2 flowing in the periods in which the secondary winding voltage V2 is clamped at a positive/negative level as shown are 35 Ap, in the same manner as in the case of the circuit in FIG. 27 (the rectified currents I1, I2 in the waveform diagrams in FIG. 28). However, the MOS-FETs Q3, Q4 are of low ON resistance, so that the conduction loss of the rectified currents can be made conspicuously lower, as compared with the rectifying diodes D01, D02 composed of Shottky diodes. In addition, as understood from the fact that the drive circuits are composed only of resistance devices, the winding voltage detection system has also the merit that the drive circuit system is simple in configuration.
However, under the condition of a heavy load (load power P0=100 W) as in the case corresponding to FIG. 30, this power circuit also has the problem that the secondary-side rectified currents are in a discontinuous mode. This is shown by the fact that, in FIG. 30 also, the periods DON1, DON2 are discontinuous.
In this discontinuous mode, even when the rectified currents I1, I2 are such that the charging current for the smoothing capacitor C0 is at zero level, a current is flowing in the same direction through the primary winding N1 of the insulated converter transformer PIT. This indicates that, in the waveform diagrams shown in FIG. 28 above, in the other periods than the periods DON1, DON2, the excitation inductance component in the primary winding N1 is flowing as the primary-side series resonance current I0 in the same polarity as that at the immediately previous timing. Therefore, in practice, the polarities of the voltages induced in the secondary windings N2A, N2B are not inverted, so that during those periods, the MOS-FETs Q3, Q4 are not perfectly turned OFF but remain in the ON state. This results in that currents in the reverse direction would flow as the rectified currents I1, I2 in the other periods than the periods DON1, DON2, as shown in the figure. The rectified currents I1, I2 in the reverse direction in the other periods than the periods DON1, DON2 generate a reactive power, and, since the level of the rectified currents I1, I2 in this instance is as comparatively high as 8 Ap, the reactive power amount is fairly large.
Thus, in the case of adopting the winding voltage detection system for the synchronous rectification circuit, the conduction loss in the rectified current is reduced, but at present it is difficult to contrive an effective enhancement of the power conversion efficiency as a whole, since the reactive power is generated as described above.
The waveform diagrams shown in FIG. 31 show the operation of a power circuit, adopting the secondary-side configuration shown in FIG. 29, under a light load condition.
In practice of the power circuit shown in FIG. 29, also, a constant voltage control based on a switching frequency control is performed, as described above as the configuration of the power circuit shown in FIG. 27. In this case, when a light load condition is obtained and the secondary-side DC output voltage increases, the switching frequency is enhanced so as to lower the secondary-side DC output voltage, thereby contriving stabilization.
In such a light load condition, the secondary-side winding voltage V2 is inverted at substantially the same timing relative to the end-to-end voltage V1 of the switching device Q2 shown in FIG. 31, and, according to this, the rectified currents I1, I2 on the secondary side flow in such a manner as to continuously charge the smoothing capacitor C0, without any rest period between the periods DON1, DON2. Namely, a continuous mode is attained. In this instance, there is no period in which the rectified currents I1, I2 in the reverse direction as shown referring to the operation under a heavy load in FIG. 30 above flow, and there is no reactive power generated according to such reverse-direction currents.
Thus, the power circuit configured by replacing the secondary-side rectification circuit system by the synchronous rectification circuit based on the winding voltage detection system also has the problem that the power conversion efficiency is lowered at the time of a heavy load.
In view of this, as a technology for solving the problem of the generation of reactive power due to the reverse-direction rectified currents, as shown in FIG. 30 above, a synchronous rectification circuit based on a rectified current detection system has been known. The rectified current detection system lies in the technology of turning OFF the MOS-FETs before the rectified currents for charging the smoothing capacitor C0 are reduced to zero level. An example of the technology is disclosed in Japanese Patent Laid-open No. 2003-111401.
A configuration example of the synchronous rectification circuit based on the rectified current detection system is shown in FIG. 32. Incidentally, in this figure, a configuration based on half-wave rectification is shown, for simplification of description.
In the rectified current detection system, a current transformer TR is provided for detecting a current flowing through a secondary winding N2. The primary winding Na of the current transformer is connected to an end portion of the secondary winding N2 and to the drain of a MOS-FET Q4. The source of the MOS-FET Q4 is connected to the negative terminal of a smoothing capacitor C0.
To a secondary winding Nb of the current transformer, a resistor Ra is connected in parallel, and diodes Da, Db are connected in parallel so that their forward voltage directions are alternately reversed, to thereby form a parallel connected circuit. In addition, a comparator 20 is connected to the parallel connected circuit. A reference voltage Vref is inputted to an inversion input terminal of the comparator 20. Incidentally, an end portion, on the side where the anode of the diode Da and the cathode of the diode Db are connected, of the parallel connected circuit is connected to the connection point between the reference voltage Vref and the inversion input terminal of the comparator 20. Besides, an end portion, on the side where the cathode of the diode Da and the anode of the diode Db are connected, of the parallel connected circuit is connected to the non-inversion input terminal of the comparator 20.
In this case, the output of the comparator 20 is impressed on the gate of the MOS-FET Q4 after being amplified by a buffer 21.
Operation waveforms of the circuit configured as shown in FIG. 32 are shown in FIG. 33.
When the voltage induced in the secondary winding N2 exceeds the end-to-end voltage (E0) of the smoothing capacitor C0, first, due to the anode→cathode direction of the body diode in the MOS-FET Q4, a rectified current Id starts to flow so as to charge the smoothing capacitor C0. Since the rectified current Id flows through the primary winding Na of the current transformer, a voltage Vnb according to the rectified current Id flowing through the primary winding Na is inducted in the secondary winding Nb of the current transformer. In the comparator 20, the reference voltage Vref and the voltage Vnb are compared with each other, and an H level is outputted when the voltage Vnb exceeds the reference voltage Vref. The H level output is impressed through the buffer 21 onto the gate of the MOS-FET Q4 as an ON voltage, thereby turning ON the MOS-FET Q4. As a result, the rectified current Id flows in the direction of the drain→source of the MOS-FET Q4. In FIG. 33, the rectified current Id is shown as flowing in positive polarity.
Then, the level of the rectified current Id is lowered as time passes, and, when the voltage Vnb is accordingly lowered below the reference voltage Vref, the comparator 20 inverts its output. With the inverted output fed out through the buffer 21, the gate capacitance of the MOS-FET Q4 is discharged, whereby the MOS-FET Q4 is turned OFF. At this time point, the residual rectified current Id flows through the body diode DD4 in a short time.
With such operations, the MOS-FET Q4 is turned OFF at a timing before the rectified current Id is reduced to zero level. This ensures that the flow of the reverse-direction current through the MOS-FET, and the attendant reactive power, in the periods in which the rectified currents are discontinuous as shown in FIG. 30 can be obviated, and the power conversion efficiency is enhanced accordingly.
For example, in the case where the secondary-side configuration of the power circuit shown in FIG. 27 was replaced by the synchronous rectification circuit based on the full-wave rectification type rectified current detection system configured as in FIG. 32, the measurement of the DC→DC power conversion efficiency under the same conditions as in FIGS. 28 and 30 and the like gave an enhanced value of about 90%.
However, in the synchronous rectification circuit based on the rectified current detection system, at least one set of current transformer and a comparatively complicated drive circuit system for driving the MOS-FET according to the output of the current transformer are required, for one MOS-FET, as is seen from FIG. 32. This complicates the circuit configuration and leads to a lowering in production efficiency, a rise in cost, an enlargement of the circuit substrate size, and the like.
Particularly, in the case where the configuration of the primary-side switching converter shown in FIG. 32 is adopted as a basis and the synchronous rectification circuit based on the rectified current detection system is provided on the secondary side, it is necessary to provide a full-wave rectification circuit on the secondary side. Therefore, the above-mentioned current transformer and drive circuit system are required respectively for each of the MOS-FETs Q3, Q4, which renders the above-mentioned problem graver.
Thus, comparing the winding voltage detection system and the rectified current detection system, the winding voltage detection system is, on one hand, disadvantageous on the basis of power conversion efficiency, due to the reactive power, but is simpler in circuit configuration; on the other hand, the rectified current detection system is advantageous in view of power conversion efficiency, due to the absence of reactive power, but is more complicated in circuit configuration. Thus, there is a trade-off relationship between the two kinds of systems.
Accordingly, it is demanded that a power circuit including a synchronous rectification circuit should have a circuit configuration as simple as possible while being free of an increase in loss due to reactive power.